发明名称 DECODER FOR RUN LENGTH LIMITED CODE
摘要 PURPOSE:To attain miniaturization by dividing an n bits into plural blocks, decoding each divided block tentatively and decoding a data word based on the combination of results to decrease the capacity of a ROM. CONSTITUTION:The code word unit is kept for a recovered code word by a serial/parallel converter 1 and a 12-bit D flip-flop 2(DFF) at first. Then the head bit of the code word stored in the DFF2 is fed to one input of an exclusive OR gate 4 via an inverter 3 and an output of the DFF2 is given as it is to the other input. Then the high-order and low-order 6 bits in the code word of a table pattern appearing at the output terminal of the gate 4 are given respectively to the address terminal of ROMs 5, 6. Finally, a 2-bit value R1 being an output of the ROM5 and a 4-bit value R2 being an output of the ROM6 are given to a ROM7, then a data word corresponding to the inputs R1 and R2 appears and it is an output of the decoder.
申请公布号 JPS61145934(A) 申请公布日期 1986.07.03
申请号 JP19840269107 申请日期 1984.12.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IKETANI AKIRA
分类号 H04L25/49;G11B20/14;H03M7/14;H03M7/46 主分类号 H04L25/49
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