| 摘要 |
PURPOSE:To attain effective buffer memory control by providing plural TAG sections managing a buffer memory and providing an inter-block identifier in the 2nd TAG section so as to apply minute control the buffer ineffective request. CONSTITUTION:A main memory controller MCU2 is provided with a TAG7 managing a buffer memory and the TAG7 has a capacity 4 times that of a TAG6 provided to a CPU3. Further, the TAG7 is provided with A-PORT8 and B-PORT9, the PORT8 is accessed only with a vector processor VU4 and the PORT9 is accessed by the VU4, a channel processor CHP5 and the CPU3. The capacity of the TAG7 is increased more than the capacity of the TAG6 and the inter-block identifier is provided in the TAG7, then the minute control of the buffer ineffective request is attained and effective buffer memory control is conducted.
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