| 摘要 |
PURPOSE:To obtain a circuit system in which plural symbol strings are identified in parallel and flexible identification is attained by changing an input speed by symbol or a drive speed of a charge transfer voltage pulse in response to the allowance. CONSTITUTION:In registering a symbol string MEMO, the symbols M, E, M, O are inputted sequentially to an address decoder 101. The 1st-3rd word lines 102 are selected and driven sequentially, control signals of 1010, 0100, 1010, 0001 are outputted in parallel from four R/W circuits 104 and inputted to a logical circuit 124. When each output of the circuits 104 is logical '1', a voltage pulse phi1 is fed to a gate G1, the electric charge in capacitors C0, C2, C4, C6 is transferred respectively to capacitors C2, C4, C6, C8. When the output of the circuits 104 is logical '0', the pulse phi1 is not fed to the G1 and the electric charge is inhibited. The gate G1 forms a quantized circuit 130, and is closed when the quantity of the electric charge fed to the capacitor C8 is a threshold value or over to generate an output signal Y falling down from a +V0 to 0 volt, the Y is inputted to an encoder 140, where it is converted into a symbol string identification code.
|
