| 摘要 |
PURPOSE:To transfer a large quantity of data including an address of the transmitting processor with a small number of data bus lines and to cope with easily when the data quantity is changed by installing a transmitting and receiving resisters in accordance with the data transferring quantity between processors. CONSTITUTION:When the transfer is executed from a processor module 1 to a processor module (n), and first, the using right of a system bus 100 is issued from an arbiter 300 through a receiving circuit 16 to a module 1, immediately it is informed that the transmitting is allocated at a transmitting circuit 14. Next, the circuit 14 synchronizes an address of a transferring processor sent already to transfer the data from CPU10 to a transmitting register 13, an address of the self-processor and respective bits of transferring data with the clock and sends them to the bus 100. Thus, the transferring data are inputted through a receiving circuit n6 of the designated module (n) to a receiving resister n5. In such a way, a large quantity of the data can be transferred with a small number of the data bus lines and even when the data quantity is changed, the coping can be easily executed. |
