发明名称 JOSEPHSON RESETTING CIRCUIT
摘要 PURPOSE:To simplify constitution of external power source and shorten cycle time of a memory circuit by providing a delaying means on the same chip with the memory circuit. CONSTITUTION:Signal line groups 11, 12, resetting gate groups 13, 14, a memory cell array 15 and a delaying means 17 are constituted as an integrated circuit on the same chip. A driving signal came out from a power source 16 is divided into two and one is applied to the signal line 12 and becomes a driving signal of the gate group 14 and becomes an address current resetting signal of a memory. Another signal passes through the delaying means 17 and applied to the signal line group 11 and becomes a driving signal of the gate group 13, and becomes a data current resetting signal of the memory. Thus, the data current resetting signal is supplied to the memory cell array delayed by the address current resetting signal, and data current is reset later than address current.
申请公布号 JPS61144796(A) 申请公布日期 1986.07.02
申请号 JP19840265454 申请日期 1984.12.18
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 HIDAKA MUTSUO
分类号 G11C11/44;H03K19/195 主分类号 G11C11/44
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