发明名称 BUFFER MEMORY CONTROLLER
摘要 PURPOSE:To use data in a buffer memory device without invalidating the data even if a page size is changed by indexing an address array without considering the page size. CONSTITUTION:A pair of conversion tables (TLB)302 for converting a logical address into a real one at a high speed and a buffer memory address array (BAA)306 for indexing where data exists in the buffer memory device are simultaneously indexed by the address of a logical address register 301 having a given logical address. The logical address is converted into a real address, and an operation until obtaining the address of the buffer memory device is executed in one machine cycle. The given logical address indexes the TLB302. At this time, if a comparator circuit 303 detects that the real address corresponding to the logical one does not exist in the TLB302, an address converting circuit 310 is activated.
申请公布号 JPS61141053(A) 申请公布日期 1986.06.28
申请号 JP19840262754 申请日期 1984.12.14
申请人 HITACHI LTD 发明人 WATABE YASUO
分类号 G06F12/08 主分类号 G06F12/08
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