发明名称 HYBRID CACHE STATE AND FILTER TRACKING OF MEMORY OPERATIONS DURING A TRANSACTION
摘要 <p>In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.</p>
申请公布号 WO2014004234(A1) 申请公布日期 2014.01.03
申请号 WO2013US46709 申请日期 2013.06.20
申请人 INTEL CORPORATION 发明人 CHAPPELL, ROBERT S.;RAJWAR, RAVI;ZHANG, ZHONGYING;BESSETTE, JASON A.
分类号 G06F12/08 主分类号 G06F12/08
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