发明名称 DATA PROCESSOR
摘要 PURPOSE:To prevent each buffer memory device against interference with each other by executing independently re-reading of an operand in correspondence to the buffer memory device. CONSTITUTION:A command from a command register 1 is decoded by a decoding circuit 2. Operand address generator circuits 3-1 and 3-2 input the operand part of the command,and calculate an operand address. In correspondence to the operand generator circuits 3-1 and 3-2 re-reading operand address cues 4-1 and 4-2 are installed. their operand addresses are selected by selectors 5-1 and 5-2, and stored in registers 6-1 and 6-2, after which they are given to a buffer memory device 10. Contents read out of the device 10 are given to an arithmetic unit through output registers 7-1 and 7-2.
申请公布号 JPS61141052(A) 申请公布日期 1986.06.28
申请号 JP19840262751 申请日期 1984.12.14
申请人 HITACHI LTD 发明人 ABE SHUICHI;WATABE SHINYA
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
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