| 摘要 |
PURPOSE:To make display and recording stable by providing a clock control circuit stopping the operation of a display control circuit so as to synchronize the picture display timing. CONSTITUTION:When an internal horizontal synchronizing signal HSYNC rises during generating period of an external horizontal synchronizing signal EXT- HSYNC, a flip-flop 91 is triggered, a low level of data terminal D is outputted to its output Q, to change an HS signal to a low level. When the EXT-HSYNC changes to a low level, the flip-flop 91 is present again and changes to a high level and since a DCLK is inputted to an AND gate together with the HS signal, the CLD signal is stopped. When the stop of the CLK signal is released, the operation of the display control circuit 5 is restarted. Thus, the timing relation is made stable.
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