| 摘要 |
PURPOSE:To attain a high communication throughput as well as the minimiazation of the operation overhead by providing independently a status communication means for inter-processor parallel processing that is regarded indispensable to the parallel processing, a hardware means and plural high-speed share memory communication means exclusive for data communication respectively. CONSTITUTION:The vase microprocessors 1-13 are connected with each other by three independent share memory bused 73-75 and a system bus 109 used mainly for connection of a common interface 95. While the parallel processing hardwares which are needed previously for parallel processing are stored to communication controllers 21-33 of each processor. Then those communication controllers are connected with each other vis a common bus 76 and an exclusive/common bus77 and independently of the common bus. |
