发明名称 Semiconductor memory addressing circuit
摘要 A semiconductor memory device used, for example, for a graphic data storage device of a graphic display apparatus and so on, in which the data is read out not only from a target memory cell designated by an input address signal but also from one or more memory cells whose locations have predetermined relationships with the target memory cell. The semiconductor memory device comprises a plurality of memory cells, a plurality of data lines, a plurality of data buses, and a data line selecting circuit. The data line selecting circuit selectively connects a selected data line designated by an address signal to a particular data bus among the plurality of data buses and connects one or more data lines whose locations have predetermined relationships to that of the selected data line to other data buses which are different from the particular data bus. The signal of a designated data line is output to the particular data bus whichever data line is designated.
申请公布号 US4597063(A) 申请公布日期 1986.06.24
申请号 US19840594630 申请日期 1984.03.29
申请人 FUJITSU LIMITED 发明人 TAKEMAE, YOSHIHIRO
分类号 G01C7/00;G06T1/60;G09G5/00;G09G5/39;G09G5/395;G11C7/00;G11C7/10;(IPC1-7):G11C8/00 主分类号 G01C7/00
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