| 摘要 |
PURPOSE:To realize high-speed random access by making access to data in such a way that digit and line address signals are implemented from an input address signal and the digit and line address signals are compared with the previous input signal and, when they coincide with each other, it is judged that the input is the first one. CONSTITUTION:An address implementing circuit 3 outputs a row address RA implemented from a supplied input address signal line 4 and a column address CA to another storage circuit 7 through another signal line 6. When an access- enable signal is supplied to a control circuit 1 from an external device, the comparator circuit 9 compares the previous row address RA and current row address RA whether they coincide with each other or not. When a coincidence signal is supplied, the control circuit 1 judges that the input is the first one and successively outputs an RAS selecting signal and CAS selecting signal to a selection circuit 11. The row address RA and column address CA from the selection circuit 11 are respectively stored in buffers 13 and 14. Access to data is performed to the line corresponding to the row address RA stored in the buffer 13 and to the position of a memory matrix 17 of the digit corresponding to the column address C.
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