| 摘要 |
PURPOSE:To make a content of cache memory coincident with that of a main storage device by clearing a cache block even when the operating speed of a CPU is slower than the operating speed of a bus. CONSTITUTION:A count-up value of counters 31,32 is inputted to a cache block clear control circuit 33 and compared, and when both values are equal, it shows that an effective write address exists in a cache memory 24. The circuit 33 outputs a signal commanding clearing of a cache clock to the memory 24 to a line 36. When the difference between the value of the counters 31,32 reaches a prescribed maximum value corresponding to the maximum capacity of an address stack 35 and a write address is inputted from the counter 31, the circuit 33 sets an FF 234. Then a part having dissidence with the content of the main storage area in the memory 24 is cleared.
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