| 摘要 |
PURPOSE:To attain data transfer between each IO controller and a DMA buffer into through a main storage device by using a direct memory access (DMA) memory part as a DMA buffer and providing it to a common bus together with a DMA controller. CONSTITUTION:In transferring a data from the input/output controllers IOC 12-14 to the DMA buffer 21, the control information such as transfer start address and byte number is set to the DMA controller by a CPU 11. Then a data is transferred via a common bus 16 under the control of the controller 15 to the DMA buffer 21 from the IOC 12-14. In transferring the data from the buffer 21 to the IOC 12-14, the reverse operation as above is executed and the data is transferred. The CPU 11 is released at data transfer between the IOC 12-14 and the buffer 12, and a main storage device MEM 20 is connected to the CPU 11 not through the common bus 16, then the data is processed between the CPU 11 and the MEM 20 in parallel with the data transfer processing. |
