| 摘要 |
PURPOSE:To reduce bus occupying time and write time required for write of same data by applying a write address and the same write data to a basic bank memory at the same time to cause the write of the same data simultaneously. CONSTITUTION:When an operation code of a write mode instruction is fed to a decoder 9 via a timing circuit 8, a signal ALL BANK WRITE is generated from the decoder 9. The signal is fed to a write data register 2 of basic bank memories B0-B7 via OR gates 50-57. Thus, the write data transmitted via a write data line 3 is set to all write data register 2. Various timing signals are generated from the circuit 9 this time to make the storage unit area to be written with a data in each memory into writable state. Since the data from the register 2 is applied in this state, the same data are written simultaneously to the storage unit areas of each bank memory.
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