| 摘要 |
PURPOSE:To make a delay of an access time due to an ECC circuit zero and to display a sufficient error detecting and correcting function by outputting the data which are not detected and corrected at the usual reading cycle and detecting and correcting the error at the time of refreshing cycles and restoring in a memory cell array. CONSTITUTION:The data read from a memory cell array 1 are quided to a control circuit 2, it is decided whether the cycle is a cycle outputted to a device external part by an external input signal to a memory device or a refreshing cycle, and when the data are outputted to the external part, the read data are sent to an output buffer circuit 3 as they are, in case of the refreshing cycle,reading data are sent to an ECC circuit 4. The output buffer circuit 3 outputs the sent data to the external part of the memory device, the ECC circuit 3 detects and corrects the error of the data sent to the refreshing cycle by means of a horizontal vertical parity system and restores the data into the memory cell array 1. |
