| 摘要 |
<p>PURPOSE:To simplify the program to realize the equivalence in capacitance without any changes in arrangement and wiring results, by adding capacitor art work patterns to one terminal of the connection circuit. CONSTITUTION:The distributed gate block of a master slice LSI is composed of a distributed gate part D made of a cell C2 and capacitor art work pattern installed parts CP1-CP4 made of cells C1, C3. The installed parts CP1, CP2 and CP3, CP4 of each cell C1, C3 of this distributed gate block are connected to the terminals P1-P4 of the distributed gate part D with connection lines lP1, lP2 and lP3, lP4, respectively. The connection lines lP1-lP4 from this part D to the parts CP1-CP4 are set so as to reduce double-layer wiring regions. Thus, the program to realize the equivalence in capacitance is simplified without any changes in arrangement and wiring results of the LSI block.</p> |
