发明名称 TRANSMISSION DELAY TIME CONTROL TYPE LOGICAL CIRCUIT
摘要 <p>PURPOSE:To obtain a transmission delay time control logic circuit realizing plural different functions by changing a signal transmission delay time of a signal transmission path. CONSTITUTION:Programmable delay circuits PDL1-PDLn are connected between signal input terminal 1-n and a sequence circuit 10. It is not always required to insert the programmable delay circuits to all signal transmission path to be connected to the sequence circuit 10, but some of them can be of fixed time by which delay time cannot be changed. The delay time of the programmable delay circuit is changed in two kinds depending on the level of the control signal. Thus, in using n-set of programmable delay circuits, the combination of the arrival orders of the signals transmitted to the sequence circuit 10 is n! (factorial n) and n! kinds of circuit functions are obtained.</p>
申请公布号 JPS61126819(A) 申请公布日期 1986.06.14
申请号 JP19840247142 申请日期 1984.11.22
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 MATSUMOTO TAKASHI
分类号 H03K19/0175;G06F1/10;H03K19/00;H03K19/20 主分类号 H03K19/0175
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