| 摘要 |
PURPOSE:To hold a highly speedy output time and secure output data by operating a data amplifier circuit from the balance condition. CONSTITUTION:Before data transfer, an FET-Q21 of a balance circuit 54 is not made conductive by a control signal EQ, and the data corresponding to lead wires 1 and 2 are amplified by a data amplifier circuit 50. Next, a Q22 and Q23 of a data transfer circuit 55 are made conductive by a control signal LH, and the data amplified at the circuit 50 are transferred to a holding circuit 56. After an FF circuit F1 of the circuit 56 holds the data, the Q22 and Q23 are made non-conductive by the control signal LH and the transfer circuit 55 is not activated. Next, the Q21 is made conductive by a control signal EQ, a balance circuit 54 is activated and the output of the amplifier circuit 50 is balanced.
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