发明名称 APPARATUS FOR TESTING INTEGRATED CIRCUIT
摘要 PURPOSE:To make it possible to form an optimum program high in mass production effect while a test program is variously altered, by counting only the overhead time of a performed program by a timer. CONSTITUTION:When a test start signal (a) is inputted, a timer 24 begins to count a time and a central processing unit 3 accesses a memory apparatus 5 to decode a test program 4. When a test order is detected, a pattern start signal (b) is sent to a pattern generation part 6 not only to indicate the running start of the test pattern but also simultaneously to interrup the time counting of the timer 2 temporarily. When the pattern generation part 6 completes the running of a pattern, the timer 2 reopones the counting of a time by a completion signal (c). The above mentioned operation is repeated every when the central processing unit 3 detects the test order and, when a test completion order is detected, the operation of the timer 2 is stopped by the stop signal (d) from a control part 1 and an overhead time is counted.
申请公布号 JPS61124874(A) 申请公布日期 1986.06.12
申请号 JP19840246612 申请日期 1984.11.21
申请人 NEC CORP 发明人 NIGORIKAWA ATSUSHI
分类号 G01R31/28;G01R31/3183;G06F11/273;H01L21/66 主分类号 G01R31/28
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