| 摘要 |
A non-volatile memory has a plurality of coupling transistors for coupling bit lines to an equalization line in response to an equalization pulse. The equalization line has capacitance as do the bit lines. Prior to the occurrence of the equalization pulse, the unselected bit lines are charged to a first predetermined voltage, and the equalization line is charged to a second predetermined voltage by a high impedance reference voltage generator. A pulse generator provides the equalization pulse in response to an address transition.
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