| 摘要 |
PURPOSE:To lessen the area needed for a contact of the high-resistance element with the low-resistance wiring and to enable to enhance the integration degree by a method wherein an etching is selectively performed on a part of the low-resistance wiring layer, the high- resistance element is formed in the interior of the groove and impurities are selectively ion- implanted in the connecting part of the low-resistance wiring layer and the high-resistance element. CONSTITUTION:A field oxide film 22 for element isolation is selectively formed on the main surface of a P-type silicon substrate 21, and after that, arsenic ions are ion-implanted to form an N<+> type diffusion layer wiring layer 23. Then, after a photo resist 24 is formed, an etching is selectively performed on a part of the N<+> type diffusion layer wiring layer 23 deeper than the junction depth using the photo resist 24 as a mask, the part thereof is removed and a groove 25 having a width (d) is formed. After the photo resist 24 is removed, a polycrystalline silicon film 26 consisting of a material for high-resistance element is deposited on the whole surface in a film thickness of half or more of the width (d) of the groove 25. Then, by performing an etchback on the whole surface as deeper as a component equivalent to the film thickness of the polycrystalline silicon film 26, a high-resistance element 27 consisting of a polycrystalline silicon film is formed only in the interior of the groove 25. By this method, the planar area needed for a contact of the high-resistance element with the low-resistance wiring is eliminated and the integration degree of the semiconductor device can be made to significantly improve. |
