发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 PURPOSE:To increase the arithmetic processing time to the data which is under a transfer state by bypassing a part necessary for an instantaneous operation to send it to an arithmetic part among those data which are transferred to a buffer memory from a main memory and merging the arithmetic result and the transferred data. CONSTITUTION:A memory control part (MCU) transfers (m) pieces of n-byte blocks including the data required for an arithmetic part 2 and not detected within a buffer memory 1. A move-in register 3 transfers (x) bytes of the head block needed instantaneously for operations to the part 2 through a BYPASS route. While the arithmetic results are sent to the MCU from a store buffer 6 via a store data register 5 as well as to a multiplexer 311 to be merged with the remaining (n-x) bytes of the head block which are not sent to the part 2. These merged bytes are written to the corresponding blocks of the memory 1 via a buffer data-in register 4.
申请公布号 JPS61118855(A) 申请公布日期 1986.06.06
申请号 JP19840241212 申请日期 1984.11.15
申请人 FUJITSU LTD 发明人 SHINOHARA TERU;OSONE HIDEKI
分类号 G06F12/08 主分类号 G06F12/08
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