| 摘要 |
PURPOSE:To attain the synchronization of multiframe by setting a phase difference between a multiframe synchronizing signal and an inner one extracted from reception data to an address difference between write and read addresses so as to give it to a variable delay RAM. CONSTITUTION:In synchronizing with the inner frame synchronizing signal 20 the count-up of the read address starts, and with the aid of an inner clock 21, write data is read out from an address specified by the read address. Accordingly, in terms of a frame aligner 2, frame data is read out in synchronizing with the inner frame synchronizing signal formed in the interior and the inner clock at the time of reading. Since a phase fluctuation lies between the phase of the frame of a reception data 10 and a reception clock 11, a main aligner at the reception side generates an inner clock 21 and an inner frame synchronizing signal 22 with the use of a PLL including a clock oscillator. If the frame aligner 2 is employed, a reception data 22 is read out so as to synchronize with the inner clock signal 21. Thus the capacity of an expensive ES and its number can be reduced, and the cost of a system can be cut. |
