| 摘要 |
PURPOSE:To realize an optional logical equation with one kind of cell and inverter by using a logical gate having four inputs and whose output shown H,L levels and high impedance depending on the combination of the inputs. CONSTITUTION:The midpoint X of CMOS FETs (M13, M14, M29, M30) and CMOS FET of the same polarity (M15, M16, M31, M32) is connected mutually. In this circuit connection tri-state (H, L levels and high impedance) is obtained by two input signals. Since an optional logic such as AND or OR is obtained depending on the combination of inputs, a full adder is constituted and the power consumption is reduced because of the adoption of CMOS. |
