发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To reduce the short channel effect of a MOS transistor by diffusing an n<-> type layer as a first electrode for a capacitor in approximately the same depth as a field groove 2 from the upper surface of an island region. CONSTITUTION:Field grooves 2 are formed to a p<-> type substrate 1 and island regions 3 are arranged and shaped, two memory cells are formed in the regions 3, insulating films 6 are shaped at the end sections of the regions 3, and capacitor electrodes 7 consisting of polycrystalline silicon films are formed while surrounding the end sections. n<-> type layers 8 are diffused in approximately the same depth as the grooves 2 from the upper surfaces of the regions 3 as first electrodes for capacitors, and p<+> type layers 9 in concentration higher than the substrate 1 are shaped to the substrate 1 so as to surround the layers 8. The p<-> type layers 12 in low concentration are formed in channel regions in MOS transistors because thresholds are increased in the channel regions in the MOS transistors in the layers 9, and gate electrodes 11 and an Al wiring 15 are shaped.
申请公布号 JPS61107763(A) 申请公布日期 1986.05.26
申请号 JP19840229210 申请日期 1984.10.31
申请人 TOSHIBA CORP 发明人 WATANABE SHIGEYOSHI;MASUOKA FUJIO
分类号 H01L27/10;H01L21/8242;H01L27/108 主分类号 H01L27/10
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