发明名称 INPUT FAULT PROCESSING SYSTEM
摘要 PURPOSE:To generate a fault alarm instantly at bit of an input by applying a self-running clock at momentary interruption of input of a phase synchronizing oscillator to which a clock extracted from a reception signal is applied to a frame synchronizing circuit so as to generate an out of synchronism signal. CONSTITUTION:The reception signal is subject to waveform correction by an equalizing circuit 1, from the output of which a clock CK component is extracted and the component is inputted to a PLL circuit 8. The CK extracted at the circuit 8 is subject to phase comparison 3 with a signal from a VCO5, and its error signal controls the VCO5 via an LPF4. Thus, the output CK of the VCO5 becomes a signal synchronously with the input CK and its output is inputted to a CK input terminal of an FF6 and a frame synchronizing circuit 7. An output waveform from the circuit 1 is fed to the FF6, which identifies the data and gives an output to the circuit 7 while taking timing. If the input signal is interrupted, since the self-running clock of the VCO5 is fed to the circuit 7, the circuit 7 keeps operation normally, generates surely a frame out of synchronism signal and an input fault alarm is raised instantly.
申请公布号 JPS61107838(A) 申请公布日期 1986.05.26
申请号 JP19840229323 申请日期 1984.10.31
申请人 FUJITSU LTD 发明人 KATO TOSHIRO
分类号 H04J3/14;(IPC1-7):H04J3/14 主分类号 H04J3/14
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