DISPOSIZIONE CIRCUITALE A TRANSISTOR MOS INTERGRATA

摘要

The source-drain resistance of an MOS load transistor (M2) is linearized by means of a pair of properly designed auxiliary MOS transistors (M3 and M4) whose source-drain paths are electrically coupled (conductively or through an amplifier) with the load transistor (M2). The gate electrode of the load transistor (M2) is connected to the common node point (N34) between the auxiliary transistors (M3 and M4); whereas the transconductances ( beta 3 and beta 4) of the auxiliary transistors (M3 and M4) are designed such that during operation the resulting feedback signal from the common node point (N34) to the gate electrode of the load transistor (M2) reduces its nonlinearity.