发明名称 INSTRUCTION DECODE SYSTEM
摘要 PURPOSE:To eliminate an overhead by connecting an operation code feed of a machine instruction register and information representing data attribute in a CPU and applying the said information to a decoder to extract quickly an inlet address of a microprogram routine. CONSTITUTION:An operation field 11a of a machine instruction register 11 of an instruction decoder system and a tag field 16a at the top of a stack 16 are connected and the result is fed an an address of a disc patch memory 12. The data tap from the memory 12 is selected by a multiplexer 13 and the result is set to a microprogram counter 14. The set value is used to access a control memory 15 and the processing is branched into a processing routine of a type using the address of the microprogram routine as an inlet. Then the machine instruction having different processing from data is executed, the data is branched at hardware decoding to eliminate the sectioning overhead and execute a machine instruction at high speed.
申请公布号 JPS61101838(A) 申请公布日期 1986.05.20
申请号 JP19840223242 申请日期 1984.10.24
申请人 FUJITSU LTD 发明人 KISHIMOTO MITSUHIRO;HATTORI AKIRA;SHINOKI TAKESHI;KIMURA YASUNORI;NIWA MASASHI
分类号 G06F9/44;G06F9/22;G06F9/26;G06F9/318 主分类号 G06F9/44
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