| 摘要 |
PURPOSE:To reduce the overhead required for controlling the synchronization of memory access using a POST instruction and WAIT instruction, by introducing a POST flag and POST state signal. CONSTITUTION:A scalar unit (SU)3 and vector unit (VU)4 can independently issue memory access requests to a main storage device (MSU)1. Namely, they can be access sources. When a storing instruction or loading instruction is issued, access transmitting sections 5 and 6 respectively transmit access requests to a storage controlling device MCU2 in accordance with the instructions. The access controlling section 11 of the MCU2 performs access control to the MSU1 in response to the access requests. When a POST instruction or WAIT instruction is issued from an instruction controlling section, access synchronism controlling sections 7 and 8 are actuated and the ordering control of memory accesses is performed by using a POST flag 9, WAIT flag 10, and POST state signal.
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