| 摘要 |
PURPOSE:To obtain a test pattern generator wherein min. inspection input is realized and testing efficiency is enhanced, by determining the optimum probability distribution of each order in supply inspection input on the basis of the architecture of a logical circuit to be inspected. CONSTITUTION:The information relating to the architecture of a processor, which is represented by the hardware planning information 511 of a register or bus and software information 512 such as the practice content of an order or the function of a control signal, is inputted. On the basis of this information, a register X having trouble most difficult to detect is found by the Marcov model formed by a Marcov model forming part 521 in such a state that the probability of each order is made same. In attention to this register X, an order is classified by a order classifying pat 523. Probability distribution is allotted to thus divided order class and inspection input based thereon is obtained to enhance the economical effect of a random test to about 100 times.
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