| 摘要 |
PURPOSE:To attain an addition operation to the operands of various data styles having different bit widths of an exponent part, by using the output of a data style indicating means to control the actions of an exponent part generating circuit, a mantissa part generating circuit, a normalization circuit, a result generating circuit, etc. CONSTITUTION:An augend register 10 and an addend register 20 store two operands of optional data styles respectively. An exponent part generating circuit 40 produces the new exponent data out of the exponent parts of both registers 10 and 20 in response to the output of a data style indicating part 30. A digit matching circuit 60 performs the digit matching for the output of a mantissa part generating circuit 50 according to the difference of output of the circuit 40. The digit matched outputs are added together by an adder 70 and normalized by a normalization circuit 80. This normalized output is led to a result generating circuit 100. |
