发明名称 PROCESSING UNIT
摘要 PURPOSE:To improve the comprehensiveness of multiplication by forming a 2<n> multiplication supporting circuit in addition to a general multiplication circuit. CONSTITUTION:A processing unit is constituted of an operation control circuit 11, a general multiplication circuit 12, a 2<n> multiplication supporting circuit 13, a shifting operation circuit 15, and a selecting circuit 14 for selecting these output results. The 2<n> multiplication supporting circuit 13 forms exponential operation data and 2<n> multiplication shifting information from the 2<n> data obtained from a data line 103 and multiplication data obtained from a data line 102 by a floating point 2<n> multiplication instruction in accordance with a signal outputted from the circuit 11 and transfers the formed results to said selecting circuit 14 through a shifting operation circuit 15. In case of a fixed point 2<n> multiplication instruction, the 2<n> value data obtained from the data line 102 are shifted through the shifting operation circuit 15 and the shifted data are transferred to the circuit 14. In case of a 2<n> multiplication instruction, the multiplication data obtained from the data line 102 are shifted and transferred. These transferred results are selected by the selecting circuit 14 and outputted 112.
申请公布号 JPS6120132(A) 申请公布日期 1986.01.28
申请号 JP19840141216 申请日期 1984.07.06
申请人 NIPPON DENKI KK 发明人 KANEKO HIDEO
分类号 G06F7/53;G06F7/483;G06F7/507;G06F7/52 主分类号 G06F7/53
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