发明名称 PROGRAMMABLE SEMICONDUCTOR DEVICE AND METHOD OF USE THEREOF
摘要 An integrated circuit array (30, 70, 110, 170) of the type having several programmable cells and first and second sets of address lines (34,38; 38,82; 82,112; 112,114; 114,116; 116,118) features programmable cells (10,20,54,160,172) having up to four possible electrical impedance states or conditions which are made possible by a plurality of rectifying semiconductor junctions (12,14;50,52) arranged in series in each cell. The four conditions are: a first in which the impedance is high in both directions; a second in which the impedance is high in one direction and low in the opposite direction; a third in which the impedance is high in the opposite direction and low in the first direction; and a fourth in which the impedance is low in both directions. The array may be made with semiconductor layers (40,42,44,45,46,48;166,168) which form series ocoupled back-to-back diodes (12,14;50,52), each diode in each cell being selectively programmable to lose its rectifying feature. The rectifying junctions may be formed from Schottky diodes. Alternate embodiments include pluralities (36,36) of layers of such programmable cells in two or more separately programmable planes, wherein each plane may have its own addressing means. …<??>Also disclosed is an integrated circuit formed as a multilayered structure (30,70,110) of deposited layers of various materials (34 to 38), including semiconductor alloy materials (40,42,44,45,46,48). The layers of semiconductor alloys are initially deposited as continuous layers. The layers are arranged to provide semiconductor interactions between at least some of the layers at several unique locations (54) within the structure, and to provide the programmable interactions in two separate subsets (36,36;120,122), each separately programmable from the other. The integrated circuit includes addressing means (34,38,82,112,114,116, 118). Programmable logic arrays can be formed out of such multilayered structures, and may include AND and OR planes (92,94), which are vertically disposed one on top of the other.
申请公布号 JPS6194357(A) 申请公布日期 1986.05.13
申请号 JP19850214391 申请日期 1985.09.27
申请人 ENERGY CONVERSION DEVICES INC 发明人 SUTANFUOODO AARU OBUSHINSUKII;ROBAATO AARU JIYONSON;BUINSENTO DEII KIYANNERA;ZUBUI YANIBU
分类号 H01L21/82;H01L21/8229;H01L27/06;H01L27/10;H01L27/102;H01L27/118;H01L29/861 主分类号 H01L21/82
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