| 摘要 |
PURPOSE:To curtail the number of shift register circuits and selector circuits, and to reduce the scale of the circuit by constituting a titled device by providing an error decision circuit for controlling an output of the first and the second selector circuits, in accordance with whether two digital signals which are sent continuously are correct or erroneous. CONSTITUTION:Two data which are sent continuously are denoted as D1, D2 (D2 is sent first), and a data stored in a shift register circuit 15 is denoted as D3. In case D1 is correct, and D2 is erroneous, a shift register circuit 11 inputs the next correct data D1 instead of the erroneous data D2. Subsequently, an error decision circuit 18 outputs a signal so that a selector circuit 12 selects an output DO1 of the shift register circuit, and also a selector circuit 13 selects an output DO3 of a shift register circuit 16. Outputs of the selector circuits 12, 13 are inputted to a one bit full adding circuit 14 and added, become (DO1+DO3), multiplied by 1/2, (DO1+DO3)/2 is inputted to the shift register circuit 16, and a mean value interpolation is executed. |
