发明名称 |
Quantizer-subtractor circuit |
摘要 |
A quantizer-subtractor circuit is provided with a input circuit for inputting an input signal and a circuit for producing a digital signal corresponding to the input signal. The quantizer-subtractor circuit contains 2n transistors. These transistors are supplied with different bias voltages by a bias circuit. A control circuit is connected to the transistors and the input circuit and controls the currents passing through the 2n transistors. A circuit produces as a subtraction output a signal corresponding to the difference between the controlled currents passing through the transistors applied with the bias voltages having odd-ordered magnitudes and the currents flowing through the transistors applied having bias voltages with the even-ordered magnitudes.
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申请公布号 |
US4584557(A) |
申请公布日期 |
1986.04.22 |
申请号 |
US19840587128 |
申请日期 |
1984.03.07 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
SUGIMOTO, YASUHIRO |
分类号 |
H03M1/44;H03M1/00;(IPC1-7):H03M1/14 |
主分类号 |
H03M1/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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