| 摘要 |
PURPOSE:To form a large capacitance having high withstanding voltage in a fine region, and to obtain a dRAM having high performance by conducting the formation of a groove in a MOS capacitance region and the burying of a field insulating film through self-alignment without etching a substrate consisting of Si. CONSTITUTION:An SiO2 mask 12 according to a predetermined pattern is shaped to a p-Si substrate 11, and buried with a p-epitaxial layer 13 in the same thickness. Etching grooves 14 are formed to the layer 13 by using a resist mask 15 bored to a capacitance forming section. The mask 15 is removed, and a capacitance electrode 17 composed of poly Si is disposed in common with the whole memory cell except a transistor region through a gate oxide film 16. Gate electrodes (word lines) 19 are shaped onto gate oxide films 18, n<+> type sources and drains 20, 21 are formed through ion implantation, and n<+> layers are connected to n layers 22 for substrate-side electrodes having previously shaped capacitances. Lastly, the surface is coated with a CVD oxide film 23, and a common Al wiring (a bit line) 24 to which openings are bored selectively is formed. According to the constitution, a dRAM having high reliability and high performance is acquired with high yield. |
