| 摘要 |
In accordance with the present invention, the circuitry of the ten bit switched capacitor digital to analog converter utilizes five binary weighted input capacitors and a digital circuit to perform multiplexing and generating the necessary timing. A combination of input capacitors and feedback capacitors give rise to an output voltage in an amount proportional to digital input bits in a binary fashion such that in the first step, the output voltage is proportional to the first five least significant bits divided by 32 and the second step the output voltage would be equal to the previous value plus a voltage proportional to the five most significant bits. Therefore, at the end of the second step, the output voltage is an analog voltage proportional to the binary input bits times the reference voltage divided by 1024.
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