发明名称 DATA ASSIGNING SYSTEM
摘要 PURPOSE:To improve the flexibility and service expansion on the structure of a signal processor by inputting a count outputted from a count means to a storage means as an address and distributing a data reached at a unit time interval to a corresponding function package based on the information designating the function package extracted from the address. CONSTITUTION:A memory 4 and a decoder 5 are inserted between a count circuit 2 and gates (3-1)-(3-n). Functional package numbers b1-bn designating function packages (1-1)-(1-n) receiving and processing data d1-dn reached in the unit time interval t0 are stored in the memory 4 in the form of a binary code form. Function packages 1-2,1-1,1-n,...,1-3 are energized sequentially based on the function package numbers b2, b1, bn,...,b3 extracted sequentially from the memory 4 synchronously with each unit time interval t1 at each frame synchronism T, and data d1-dn reaching at the unit time interval t0 are subject to reception processing. Thus, the data d1-dn are shared into optional packages 1-1-1-n by designating optionally the function package number stored in the memory 4.
申请公布号 JPS6179396(A) 申请公布日期 1986.04.22
申请号 JP19840201240 申请日期 1984.09.26
申请人 FUJITSU LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KURODA KIYOHIKO;NAKAJIMA AKIHISA;NARUSE HIDEO;KAWAMURA TOSHIYUKI
分类号 H04Q1/457;H04Q1/45;H04Q11/04 主分类号 H04Q1/457
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