DATA COMMUNICATION SYSTEMS

摘要

The 16 kbit/s HDLC formatted signalling channel for each of 256 ISDN subscribers is separated from the data channel(s) at the exchange line circuit and TMD multiplexed into a 4 Mbit/s stream provided to a common signalling handler. In the handler, a receiving element processes each new bit of the 4 Mbit/s stream with 47 bits read out of a channel parameter store by a channel number provided by a channel allocation store. The 47 bits include the previous 7 received bits and a message byte address for that channel. When those 7 bits and the new bit form a new deformatted message byte, that byte is written into an incoming message store at a location determined by the current channel number and message byte address. Using a FIFO buffer, messages are read from the incoming message store by a processor in the order in which they are completed.