| 摘要 |
PURPOSE:To automatically correct an erroneous output of a frame synchronizing signal which is outputted by means of a false synchronizing signal, by providing a synchronization hold inspecting circuit and always inspecting the rightness of frame synchronizing signals. CONSTITUTION:A synchronizing bit pattern detecting circuit 4 takes the bit correlation between a digital input signal and synchronizing bit pattern and sends a subframe synchronizing signal (b) to a synchronism securing circuit 5 and synchronization hold inspecting circuit 9. The circuit 5 takes the correlation between frames from the signal (b) and outputs a main frame synchronizing signal (f). An 1-frame counter circuit 6 outputs an inspecting signal (d) of one frame to the circuit 5 and, under the self-running mode, a frame synchronizing signal (c) instead of the signal (f). The circuit 9 starts synchronism inspecting operations immediately after the synchronism is secured and, when the signal (f) rises, resets the circuit 6 by outputting a signal (g) and resets the initial value of the counter. At the same time, the circuit 9 commands the circuit 5 to secure the synchronism again. The circuit 5 stops the operation of the circuit 9 by outputting an operation inhibiting signal (e) to the circuit 9 and, at the same time, causes a selection switch 10 to select the signal (c). |
