| 摘要 |
PURPOSE:To detect a synchronizing signal comprising a pattern whose head and end are logical 1 or 0 and whose middle position is logical 0 or 1 by providing a 1-0 detection circuit, a 0-1 detection circuit and a counter circuit giving an output with a specified bit width. CONSTITUTION:The 1-0 detection circuit 13 detects a 0 pattern of the synchronizing signal and gives the result of detection to a counter circuit 20. The counter circuit 20 has a 1-bit width output OUT1 and a synchronizing signal detection specified output OUT2. Then the counter circuit 20 outputs a permissible output 25 for 1-bit width when the 0 pattern of the synchronizing signal is consecutive for a detection specified value. When the level of the synchronizing signal reaches logical 1 during this time, the 0-1 detection circuit 15 is set and the synchronizing detection signal 12 is outputted. Thus, the synchronizing signal comprising a pattern in which the head and end are logical 1 or 0 and the middle position is logical 0 or 1 is detected with high accuracy. |
