| 摘要 |
<p>PURPOSE:To shorten an access time by accessing simultaneously plural memory cells at peripheral address having a prescribed relation with the address specified by an access command as a center. CONSTITUTION:A memory device is constituted of 1st-4th memory blocks 1-4, data bus selection circuit 6 and data bus 7. Receiving row address signals b6y a random access action, respective blocks 1-4 act in parallel, and the side of the data bus selection circuit 6 decides any one of them to be accessed. When the block 1-4 input and output data to the memory cell of a selective word line in parallel, memory cells at adjacent row addresses are accessed in paralllel.</p> |
