| 摘要 |
PURPOSE:To enable the increase in capacitance by reducing the memory cell occupation area and securing a sufficient MOS capacitor capacitance by a method wherein a plurality of memory cell regions are formed in projection arrangement without completely filling grooves formed in the field region of a semiconductor substrate with insulation films. CONSTITUTION:The grooves 4 are formed in the field region of a p type Si substrate 1, and a MOS capacitor electrode 12 common to all memory cells is formed in these memory cell regions which form projection type memory cell regions via the first gate insulation film, and a window 13 is opened in the MOS capacitor electrode 12 at the MOS transistor region, where the gate electrode 15 of the MOS transistor is formed via the second gate insulation film 14. The MOS capacitor electrode 12 is made opposed to the outer walls of the projection type memory cell regions and to the inner walls by providing the grooves 5 in the memory cell regions. The grooves 4 of the field regions and the grooves 5 of the memory cell region are filled with thick insulation films 7 at bottoms in such a manner that the films do not completely fill these grooves. |
