| 摘要 |
A processor, for providing a double line-rate video signal comprising alternating received lines and interpolated lines, comprises a triad of memories. As each incoming video signal is stored in one of the three memories, the remaining two are read at double the write clock rate. An output circuit interleaves a non-interpolated time compressed line of video obtained from one of the two memories being read with a time-compressed line of video obtained by interpolation from both of the two memories being read to provide a processed video output signal. The write-one read-two memory organization enables concurrent interpolation and speed-up of the video signal thereby minimizing potential clock timing problems inherent in progressive scan systems of the type where interpolation is provided separately either before or after video speed-up.
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