Integrated logic circuit having collector node with pull-up and clamp

摘要

A logic circuit of the I2L, the ISL or the STL type having a signal input formed by the control electrode of an inverter transistor and plural signal outputs each coupled through a diode to a main electrode of the inverter transistor, this main electrode being connected to a supply line through a pull-up connection. The improvement relates to a further connection path comprising a Schottky diode and a resistor which bridges the main current path of the inverter transistor and which reduces the voltage swing at the main electrode.