发明名称 ANALYSIS DATA PROCESSING SYSTEM
摘要 PURPOSE:To make a whole system highly speedy by installing a bus switch so that a bus line of respective microprocessors can be released to an I/O device. CONSTITUTION:Bus switches BS1-BS4 are connected between an I/O device 5 and respective microprocessors 1-4, and a bus of respective microprocessors 1-4 can be released to one I/O device. For example, when data are fetched into the microprocessor 4, the bus switch is on and the I/O device is linked directly to the microprocessor 4. As the result, by flowing of data like the I/O device 5 and the microprocessor 4, the data are by-passed without passing through microprocessors 1-3 and RAM6-8, and fetched and processed to the microprocessor 4. Thus, a flow of the data is shortened and processing is made highly speedy.
申请公布号 JPS6152767(A) 申请公布日期 1986.03.15
申请号 JP19840174509 申请日期 1984.08.22
申请人 JEOL LTD 发明人 MINEGISHI MASAO
分类号 G06F15/16;G06F13/40;G06F15/173;G06Q50/00;G06Q50/10 主分类号 G06F15/16
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