Pulse length digital indicator circuit - employs first timing signal whose periods are counted and second timing signal fixing pulse length measuring

摘要

The pulse-length digital indication circuit has an AND gate (1) whose first input (11) receives the pulse train (P) and whose second input (12) receives a timing spiral (F1). The counting input (21) of a forward counter (2) is connected to the AND gate output (13). Storage inputs of a memory (3) are connected to the outputs of the counter. The counting input (41) of a reverse counter is also connected to the gate output. The first and a second timing signal are fed to the inputs (51, 52) of a shift register (5). A monitoring circuit (6) covers a range of successive counter positions. The first input (71) of a second AND gate (7) is connected to the shift register output and its second input (72) to the monitoring circuit output (63).