| 摘要 |
PURPOSE:To decrease the number of elements and to reduce remarkably delay time by inputting an augend, addend and a carry signal of positive correction to a gate of a transfer gate and an input gate of a series connection circuit and obtaining a sum signal while inverting the output. CONSTITUTION:Eight transfer gates T1-T8 constitute four series connection circuits each comprising two transfer gates and outputs nodes are connected in common to complementary inverters I4 being output gates. Through the constitution above, carry signals C, C' are inputted to the input node of the series connection circuits each comprising two transfer gates from the lower- order of positive correction, augends A, A' are connected to one gate of the two transfer gates connected in series and addends B, B' of positive correction are inputted to the other gates. The output signal of the output node is inverted by the output gate and a sum signal Su among the augends, addends and carry signals is obtained. |
