| 摘要 |
PURPOSE:To obtain a carry logical circuit having a small number of elements by attaining the direct transmission of the carry signal to the upper digits from lower digits as long as both the arithmetic signal and the signal to be operated are set at levels excluding ''0'' or ''1''. CONSTITUTION:When the arithmetic signal A and the signal B to be operated have different levels, either one of o channel MOS transistors 41 and 42 is turned off together with either one of n channel MOS transistors 43 and 44. Thus no current path is formed between an output terminal 23 of a CMOS inverter 20 and a point of application of VDD or VSS owing the those transistors. Therefore, the carry signal Cin given from a lower digit and supplied to the inverter 20 is delivered as it is through a CMOS inverter 30 in the form of a signal Cout. |
